With continued scaling down of devices, various challenges arise in device manufacture. For example, when the gate length is smaller than, for example, 20 nm, a gate is very difficult to be formed. Furthermore, in this case, it is extremely difficult to control Line Edge Roughness (LER) of the gate.
It is known that the LER may be improved by Spacer Transfer Image (STI) technology. However, it is difficult for STI technology to create gate structures with different gate lengths simultaneously, thereby its application is limited or the manufacturing cost is increased.